To our knowledge, no previous work has proposed re-ordering mechanisms at the network level to {\it exploit}
the problem of longer write latency in STT-RAMs. Here, we briefly describe the most closely related
previous works.

Desikan et al. in~\cite{MRAM:DLK+02, MRAM:DKB02} explored on-chip toggle-mode MRAM as a replacement
of DRAM to improve the memory bandwidth and latency. Dong et al.~\cite{xydong-dac} studied the
STT-RAM circuit design and presented a performance, power, and area model for STT-RAM caches and
analyzed the benefits of 3D-stacked STT-RAMs at an architecture level. Sun et al.~\cite{gsun-hpca}
tackled the STT-RAM write problem by using a read-preemptive write buffer technique that allows read
operations to terminate ongoing write operations under certain conditions. Zhou et
al.~\cite{MRAM:ICCAD09:Zhou} discussed the circuit design for STT-RAM early write termination to
reduce STT-RAM write overhead in details. Our work is architecturally different from Zhou et al.'s
work in the sense that we try to leverage an on-chip network to handle the write problem and is
simpler than introducing additional gates for detection and termination of writes inside each STT-RAM
sub-banks as proposed by them. Additionally, our proposal can complement the read-preemption scheme
as proposed in~\cite{gsun-hpca} by having the {\it network} prioritize reads over writes to the same
bank rather than having the bank controller perform this prioritization. Overall, none of the
previous works have leveraged the NoC design to mitigate the longer write delay problem in STT-RAMs.
